1. Field of the Invention
The present invention relates to an EL panel in which EL elements formed on a substrate are enclosed between the substrate and a cover material. Further, the present invention relates to an EL module in which an IC is mounted in the EL panel. Note that EL panels and EL modules are referred to generically by the term xe2x80x9cself light emitting devicexe2x80x9d in this specification. In addition, the present invention relates to electronic devices using the self light emitting device.
2. Description of the Related Art
EL elements have high visibility because light is self emitted, and are optimal for making a display thin because a backlight like used for an liquid crystal display (LCD) is not required. Along with this, their angle of view has no limits. Self light emitting devices using EL elements have thus come under the spotlight as substitute display devices for CRTs and LCDs.
EL elements have a layer containing an organic compound in which electro luminescence is generated by adding an electric field (hereafter referred to as an EL layer), an anode, and a cathode. There is emission of light in the organic compound in returning to a base state from a singlet excitation state (fluorescence), and in returning to a base state from a triplet excitation state (phosphorescence), and the self light emitting device of the present invention may use either type of light emission.
Note that all layers formed between the anode and the cathode are defined as EL layers in this specification. Specifically, layers such as a light emitting layer, a hole injecting layer, an electron injecting layer, a hole transporting layer, and an electron transporting layer are included as EL layers. An EL element basically has a structure in which an anode, a light emitting layer, and a cathode are laminated in the stated order. In addition to this structure, the EL element may also have a structure in which an anode, a hole injecting layer, a light emitting layer, and a cathode are laminated in the stated order, or a structure in which layers such as an anode, a hole injecting layer, a light emitting layer, an electron transporting layer, and a cathode are laminated in the stated order.
Furthermore, an EL element emitting light is referred to as the EL element being driven in this specification. Moreover, an element formed by an anode, an EL layer, and a cathode is referred to as an EL element within this specification.
There are mainly analog drive and digital drive as methods of driving a self light emitting display device which has EL elements. In particular, with respect to the digital drive, it is possible to display an image using a digital video signal with image information (digital video signal) without converting it to analog, corresponding to a digitalized broadcast signal, and therefore the digital drive is promising.
A surface area division driving method and a time division driving method can be given as driving methods for performing gray scale display in accordance with two voltage values of a digital video signal.
The surface area division driving method is a driving method for performing gray scale display by dividing one pixel into a plurality of sub-pixels and driving each sub-pixel independently based upon a digital video signal. One pixel must be divided into a plurality of sub-pixels with this surface area driving method. In addition, it is also necessary to form pixel electrodes corresponding to each of the sub-pixels in order to drive the divided sub-pixels independently. Thus, a difficulty that the pixel structure is complex develops.
On the other hand, the time division driving method is a driving method for performing gray scale display by controlling the length of time during which pixels are turned on. Specifically, one frame period is divided into a plurality of sub-frame periods. Each pixel is then placed in a turned on or turned off state in each sub-frame period in accordance with a digital video signal. The gray scale of a certain pixel is found by summing lengths of all the sub-frame periods that the pixel is turned on during, of the sub-frame periods within one frame period.
In general, the response speed of organic EL materials is fast compared to liquid crystals and the like, and therefore organic EL materials are suitable for time division driving.
A case of displaying mid-level gray scales by time division driving in accordance with a simple binary code method is explained in detail below using FIGS. 27A and 27B.
FIG. 27A shows a pixel portion of a general self light emitting device, and the lengths of all sub-frame periods within one frame period in the pixel portion are shown in FIG. 27B.
An image is displayed using a 6 bit digital video signal which is capable of displaying 1 to 64 gray scales in FIGS. 27A and 27B. The right half portion of the pixel portion performs displaying of 33rd (32+1) gray scale, and the left half of the pixel portion performs displaying of 32nd (31+1) gray scale.
Six sub-frame periods (sub-frame periods SF1 to SF6) generally appear within one frame period in the case of using a 6 bit digital video signal. The first to the sixth bits of the digital video signal correspond to the sub-frame periods SF1 to SF6, respectively.
The ratio of lengths of the sub-frame periods SF1 to SF6 become 20::21::22::23::24::25. The length of the sub-frame period SF6 corresponding to the most significant bit (the sixth bit in this case) of the digital video signal is the longest, and the length of the sub-frame period corresponding to the least significant bit (the first bit) of the digital video signal is the shortest.
For a case of performing display of the 32nd gray scale, the pixels are placed in an on state in the sub-frame periods SF1 to SF5, and the pixels are placed in an off state during the sub-frame period SF6. Further, the pixels are placed in a turned off state during the sub-frame periods SF1 to SF5, and are turned on during the sub-frame period SF6, when performing display of the 33rd gray scale.
A pseudo contour may be visible at a boundary portion between the portion for performing display of the 32nd gray scale and the portion for performing display of the 33rd gray scale.
The term pseudo contour refers to an unnatural contour line which is repeatedly visible in performing time gray scale display in accordance with a binary code method, and it is considered that the main cause is fluctuations develop in the perceived brightness due to the characteristics of human sight. A mechanism for the generation of the pseudo contour is explained using FIGS. 28A and 28B.
FIG. 28A shows a pixel portion of a self light emitting device in which a pseudo contour develops, and FIG. 28B shows the ratio of the lengths of sub-frame periods within one frame period.
An image is displayed using a 6 bit digital video signal which is capable of displaying 1 to 64 gray scales in FIGS. 28A and 28B. The right half portion of the pixel portion performs displaying 33rd gray scales, and the left half of the pixel portion performs displaying 32nd gray scales.
The pixels are placed in an on state during 31/63 of one frame period, and are placed in an off state during 32/63 of the one frame period, in the portion of the pixel portion for performing the 32nd gray scale. Periods during which the pixels are turned on appear alternately with periods in which the pixels are turned off.
Further, the pixels are placed in an on state during 32/63 of one frame period, and the pixels are placed in an off state during 31/63 of the one frame period, in portions of the pixel portion for performing the 33rd gray scale. Periods during which the pixels are turned on appear alternately with periods in which the pixels are turned off.
In a case of displaying a moving image, the boundary between portions for displaying the 32nd gray scale and portions for displaying the 33rd gray scale in FIG. 28A is taken, for example, as moving in the direction of the dotted line. Namely, the pixels switch over from displaying the 32nd gray scale to displaying the 33rd gray scale near the boundary. Then, a turn on period for displaying the 33rd gray scale begins immediately after a turn on period for displaying the 32nd gray scale in pixels near the boundary. The human eye thus can see the pixels turned on continuously during one frame period. This is thus perceived as an unnatural bright line on the screen.
Conversely, the boundary between the portions for displaying the 32nd gray scale and the portions for displaying the 33rd gray scale in FIG. 28A is taken, for example, as moving in the direction of the solid line. Namely, the pixels switch over from displaying the 33rd gray scale to displaying the 32nd gray scale near the boundary. Then, the turn on period for displaying the 32nd gray scale begins immediately after the turn on period for displaying the 33rd gray scale in pixels near the boundary. The human eye thus can see the pixels turned off continuously during one frame period. This is thus is perceived as an unnatural dark line on the screen.
The above unnatural bright lines and dark lines appearing on a screen are display obstructions referred to as pseudo contours(moving pseudo contours).
Display obstructions may also become visible in static images due to the same cause as that by which the moving pseudo contours are developed in moving images. The display obstructions in static images are ones in which flickering motion can be seen in the boundaries of gray scales. A simple explanation of the reason why such display obstructions are visible in static images is described below.
Even if a person""s eye is fixed upon one point, the visual point moves slightly, and it is difficult to stare at one point with certainty. Therefore, even if an intention is to stare at the border between portions of the pixel portion in which the pixels are performing display of the 32nd gray scale and portions in which the pixels are performing display of the 33rd gray scale when staring at the boundary, the visual point will move slightly left and right, up and down.
For example, assume that the visual point moves from portions performing display of the 32nd gray scale to portions performing display of the 33rd gray scale, as shown by the dashed line. In a case in which the pixels are in a turned off state when the visual point is located in the portions displaying the 32nd gray scale and the pixels are in a turned off state when the visual point is located in the portions displaying the 33rd gray scale, the pixels are seen to be in a turned off state through the entire one frame period by an observer""s eyes.
Conversely, for example, assume that the visual point moves from portions performing display of the 33rd gray scale to portions performing display of the 32nd gray scale, as shown by the solid line. In a case in which the pixels are in a turned on state when the visual point is located in portions displaying the 32nd gray scale and the pixels are in a turned on state when the visual point is located in portions displaying the 33rd gray scale, the pixels are seen to be in a turned on state through the entire one frame period by an observer""s eyes.
The pixels are therefore seen by human eyes to be in a turned on state, or in a turned off state, throughout one frame period because of the tiny movement to the left and right, up and down, of the visual point, and a display obstruction in which the boundary portion is seen to sway back and forth is seen.
The applicants of the present invention divided sub-frame periods with long periods in order to prevent pseudo contours from being seen. The sub-frame periods which are divided (divided sub-frame periods) are then distributed within one frame period so as not to appear in succession.
There may be one sub-frame period to be divided, and there may be a plurality of sub-frame periods to be divided. However, it is preferable that the division be performed in order from a sub-frame period corresponding to the most significant bit, in other words the longest sub-frame period.
Further, it is possible for a designer to appropriately select the number of divisions of sub-frame periods. It is preferable, however, that the number of divisions be determined by the balance between the driving speed for a self light emitting device and the required display quality of an image.
Furthermore, it is preferable that the lengths of divided sub-frame periods, corresponding to the same bit of a digital video signal, be the same, although the present invention is not limited to such. It is not always necessary to make the lengths of the divided sub-frame periods the same.
The above stated driving method is realized by forming memory within each pixel.
In accordance with the above structure, display obstructions such as pseudo contours, which are conspicuous in time division driving with a binary code method, can be prevented from being visible. The reason for such is explained below.
FIG. 1A shows a pixel portion of a self light emitting device, and the ratio of the lengths of sub-frame periods SF to appear during one sub-frame period (F) in the pixel portion are shown in FIG. 1B.
An image is displayed with FIGS. 1A and 1B using an n-bit digital video signal which is capable of displaying 1 to 2n gray scales. The right half portion of the pixel portion performs displaying 2nxe2x88x921+1 gray scale, and the left half portion performs displaying 2nxe2x88x921 gray scale.
In a case of using the n-bit digital video signal in accordance with a simple binary code method, n sub-frame periods SF1 to SFn appear within one frame period. The first bit of the digital signal to the n-th bit of the digital video signal correspond to the sub-frame periods SF1 to SFn, respectively.
The ratio of lengths of the sub-frame periods SF1 to SFn become 20::21::22:: . . . 2nxe2x88x922::2nxe2x88x921. The length of the sub-frame period SFn corresponding to the most significant bit (the n-th bit in this case) of the digital video signal is the longest, and the length of the sub-frame period SF1 corresponding to the least significant bit (the first bit) of the digital video signal is the shortest.
In a case of performing display of the 2nxe2x88x921 gray scale, the pixels are placed in an on state in the sub-frame periods SF1 to SF(nxe2x88x921), and are placed in an off state during the sub-frame period SFn. Further, the pixels are placed in a turned off state during the sub-frame periods SF1 to SF(nxe2x88x921), and are turned on during the sub-frame period SFn, in performing display of the 2n+1+1 gray scale.
The sub-frame period SFn which is the longest sub-frame period, is then divided into two divided sub-frame periods. Note that although the sub-frame period SFn is divided into two divided sub-frame periods here, the present invention is not limited to this number. The sub-frame period may be divided into any number as long as the operation speeds of a driving circuit and pixel TFTs can keep up therewith.
The sub-frame periods which are divided (divided sub-frame periods) do not appear in succession. A sub-frame period corresponding to another bit of the digital video signal always appears between the divided sub-frame periods.
Note that the lengths of the divided sub-frame periods may not all be the same. Further, it is not necessary to place any limitations on the order of the sub-frame periods. There are no limitations of setting the order from the sub-frame period corresponding to the most significant bit, to the sub-frame period corresponding to the least significant bit.
FIG. 2A shows a pixel portion of a self light emitting device for performing display by a driving method of the present invention, and FIG. 2B shows the lengths of sub-frame periods and divided sub-frame periods to appear within one frame period, which are divided into turn on periods and turn off (non-turn on) periods.
The right half portion of the pixel portion performs display of 2nxe2x88x921+1 gray scale, and the left half portion performs display of 2nxe2x88x921 gray scale in FIG. 2A.
In portions of the pixel portion performing display of 2nxe2x88x921 gray scale, the pixels are placed in an on state in (2nxe2x88x921xe2x88x921)/2n periods within one frame period, and the pixels are placed in an off state in 2nxe2x88x921/2n periods within the one frame period. The periods during which the pixels are in an turn on state and the periods during which the pixels are in a turn off state then appear alternately.
Further, in portions of the pixel portion performing display of the number 2nxe2x88x921+1 gray scale, the pixels are placed in a turned on state in 2nxe2x88x921/2n periods within one frame period, and the pixels are placed in a turned off state in (2nxe2x88x921xe2x88x921)/2n periods within the one frame period. The periods during which the pixels are in a turned on state and the periods during which the pixels are in a turned off state then appear alternately.
The visual point of an observer may move slightly left and right, up and down, and it is sufficiently possible to occasionally straddle other sub-frame periods or divided sub-frame periods. In this case, even if the visual point of an observer is fixed continuously on only turned off pixels, or conversely is fixed continuously on only turned on pixels, the turn on periods and the turn off periods during one frame period are divided and appear alternately. Thus, the lengths of successive turn on periods or turn off periods are therefore short compared with conventional driving with a simple binary code method, and pseudo contours can thus be prevented from being visible.
For example, the visual point is taken as moving from a portion displaying the 2nxe2x88x921 gray scale to a portion displaying the 2nxe2x88x921+1 gray scale, as shown the dotted line. With the driving method of the present invention, even if the pixels are in a turned off state when the visual point is located in portions displaying the 2nxe2x88x921 gray scale and the pixels are in a turned off state when the visual point moves to portions displaying the 2nxe2x88x921+1 gray scale, the sum of two turn off periods in succession becomes shorter than that for a conventional driving method. Therefore, the visualization by human eyes that the pixels are always in a turned off state throughout one frame period can be prevented.
Conversely, for example, the visual point is taken as moving from a portion displaying the 2nxe2x88x921+1 gray scale to a portion displaying the 2nxe2x88x921 gray scale. With the driving method of the present invention, even if the pixels are in a turned on state when the visual point is located in portions displaying the 2nxe2x88x921+1 gray scale and the pixels are in a turned on state when the visual point moves to portions displaying the 2nxe2x88x921+1 gray scale, the sum of the two turn on periods in succession becomes shorter than that for a conventional driving method. Therefore, the visualization by human eyes that the pixels are always in a turned on state throughout one frame period can be prevented.
In accordance with the above structure, display obstructions such as pseudo contours, which are conspicuous in time division drive with a binary code method, can be prevented from being visible.
Structures of the present invention are shown below.
In accordance with the present invention, there is provided a self light emitting device which comprises a plurality of pixels, each pixel comprising: an EL element; a memory; a first TFT; a second TFT; and a third TFT formed therein, characterized in that:
a digital video signal is input to one of a source region and a drain region of the first TFT, while the other is connected to a gate electrode of the third TFT;
one of a source region and a drain region of the second TFT is connected to the memory, while the other is connected to the gate electrode of the third TFT; and
a source region of the third TFT is connected to a first electric power source, and a drain region of the third TFT is connected to the EL element.
In accordance with the present invention, there is provided a self light emitting device which comprises a plurality of pixels, each pixel comprising: an EL element; an SRAM; a first TFT; a second TFT; and a third TFT formed therein, characterized in that:
a digital video signal is input to one of a source region and a drain region of the first TFT, while the other is connected to a gate electrode of the third TFT;
one of a source region and a drain region of the second TFT is connected to the SRAM, while the other is connected to the gate electrode of the third TFT; and
a source region of the third TFT is connected to a first electric power source, and a drain region of the third TFT is connected to the EL element.
In accordance with the present invention, there is provided a method of driving a self light emitting device which comprises a plurality of pixels, each pixel comprising an EL element, a memory, a first TFT, a second TFT, and a third TFT formed therein,
the method comprises:
a period during which a p bit of a digital signal is input to a gate electrode of the third TFT through the first TFT, and during which the p bit of the digital signal is written into the memory through the first TFT and the second TFT;
a period during which a q bit of the digital signal is input to the gate electrode of the third TFT through the first TFT, and during which the p bit of the digital signal written into the memory is stored; and
a period during which the p bit of the digital signal stored in the memory is read out, and then input to the gate electrode of the third TFT, characterized in that
light emission of the EL element is controlled by controlling switching of the third TFT in accordance with the p bit of the digital signal and the q bit of the digital signal.
In accordance with the present invention, there is provided a method of driving a self light emitting device which comprises a plurality of pixels, each pixel comprising: an EL element; a memory; a first TFT; a second TFT; and a third TFT formed therein, characterized in that:
input of a digital video signal to the pixel is controlled by the first TFT;
write in to the memory and read out from the memory of a portion of bits of the digital video signal input is controlled by the second TFT;
switching of the third TFT is controlled in accordance with the portion of bits of the digital video signal read out from the memory or the digital video signal input to the pixel; and
light emission of the EL element is controlled by the third TFT.
In accordance with the present invention, there is provided a method of driving a self light emitting device which comprises a plurality of pixels, each pixel comprising an EL element and a memory formed therein, characterized in that:
a plurality of sub-frame periods are formed in one frame period;
at least one sub-frame period from among the plurality of sub-frame periods comprises a plurality of divided sub-frame periods;
a digital video signal is written into the memory in at least one divided sub-frame period from among the plurality of divided sub-frame periods;
the digital video signal is read out from the memory in the divided sub-frame period which appears after the divided sub-frame period during which the digital video signal is written into the memory; and
light emission from the EL element is controlled in accordance with the digital video signal input to the pixel or the digital video signal read out from the memory.
In accordance with the present invention, there is provided a method of driving a self light emitting device comprises a plurality of pixels, each pixel comprising an EL element, an SRAM, a first TFT, a second TFT, and a third TFT formed therein,
the method comprises:
a period during which a p bit of a digital signal is input to a gate electrode of the third TFT through the first TFT, and during which the number p bit of the digital signal is written into the SRAM through the first TFT and the second TFT;
a period during which a q bit of the digital signal is input to the gate electrode of the third TFT through the first TFT, and during which the p bit of the digital signal written into the SRAM is stored; and
a period during which the p bit of the digital signal stored in the SRAM is read out, and then input to the gate electrode of the third TFT, characterized in that
light emission of the EL element is controlled by controlling switching of the third TFT in accordance with the p bit of the digital signal and the number q bit of the digital signal.
In accordance with the present invention, there is provided a method of driving a self light emitting device which comprises a plurality of pixels, each pixel comprising an EL element, an SRAM, a first TFT, a second TFT, and a third TFT formed therein, characterized in that:
input of a digital video signal to the pixel is controlled by the first TFT;
write in to the SRAM and read out from the SRAM of a portion of bits of the digital video signal input is controlled by the second TFT;
switching of the third TFT is controlled in accordance with the portion of bits of the digital video signal read out from the SRAM or the digital video signal input to the pixel; and
light emission of the EL element is controlled by the third TFT.
In accordance with the present invention, there is provided a method of driving a self light emitting device which comprises a plurality of pixels, each pixel comprising an EL element and an SRAM, characterized in that:
a plurality of sub-frame periods are formed in one frame period;
at least one sub-frame period from among the plurality of sub-frame periods comprises a plurality of divided sub-frame periods;
a digital video signal is written into the SRAM in at least one divided sub-frame period from among the plurality of divided sub-frame periods;
the digital video signal is read out from the SRAM in the divided sub-frame period which appears after the divided sub-frame period during which the digital video signal is written into the SRAM; and
light emission from the EL element is controlled in accordance with the digital video signal input to the pixel or the digital video signal read out from the SRAM.
The present invention may also have a characteristic in that the memory has three n-channel TFTs and three p-channel TFTs.
The present invention may also have a characteristic in that a gate electrode of one of the three n-channel TFTs is connected to a gate electrode of the first TFT, and a gate electrode of one of the three p-channel TFTs is connected to a gate electrode of the second TFT of a different pixel.
The present invention may also have a characteristic in that:
the memory has two sets of an n-channel TFT and a p-channel TFT which have gate electrodes mutually connected;
drain regions of the n-channel TFT and the p-channel TFT are mutually connected;
the gate electrodes of one of the two sets of the n-channel TFT and the p-channel TFT are mutually connected to the drain regions of the other; and
the drain regions of one of two sets of the n-channel TFT and the p-channel TFT are connected to one of a source region and a drain region of the second TFT.
The present invention may also have a characteristic in that the SRAM has two n-channel TFTs and two p-channel TFTs.
The present invention may also have a characteristic in that:
the SRAM has two sets of an n-channel TFT and a p-channel TFT whose gate electrodes are mutually connected;
drain regions of the n-channel TFT and the p-channel TFT are mutually connected;
the gate electrodes of two sets of the n-channel TFT and the p-channel TFT are mutually connected to another pair of the drain regions; and
any one of the pair of the drain regions out of two sets of the n-channel TFT and the p-channel TFT are connected to one of a source region or a drain region of the second TFT.
The present invention may also have a characteristic in that the plurality of divided sub-frame periods need not appear in sequence with the present invention.